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FUNCTIONAL DEVICE OPERATION
INITIALIZATION REQUIREMENTS
INT
SPI
CS
Px_HS
Px_LS
EN1-2
RST
VDD
VLS
VPWR
VSUP
t PU_VDD
t PU_VLS
t 1
t 2
t 3
t 4
t 5
t 6
Figure 20. Full Initialization
Table 18. Full Initialization Timing Description
Time
t PU_VDD ,
t PU_VLS
Description
Power up time from RESET
Min
2.0 ms
Comments
RESET must remain high long enough for VDD and VLS to reach the full regulated
voltage. The normal time for this to occur is specified as 2.0 ms maximum. If there is
more capacitance on VLS or VDD than the normal values given in the specification, this
time may need to be increased. In general, the time may be safely scaled linearly with
the capacitance. If the charge pump is used it may also increase this time. An estimate
of increased time, due to the charge pump, would be to add 25%. For example, the
nominal VLS capacitance is 2.2 μF on each pin, the power up time should be increased
to 4.0 ms, 5.0 ms if using the charge pump.
t 1
End of SPI communication to
EN1 and EN2 rising edge
0 ns
t 2
t 3
t 4
EN1 and EN2 rising edge to
first LS output command
Initial LS ON period
LS OF to HS ON
280 ns
1.0 μs
0 ns
Restricted by EN1 and EN2 propagation delay
Nominally 1.0 μs is more that enough. The calculated value is 5*C boot (R SENSE +
R DSON_LS ). 100 ns for default recovery.
No defined maximum, but HS is undefined until beginning of toggle on the HS
t 5
Initial HS ON period
100 ns + Minimum: Dead-time + 100 ns to guarantee the HS is switched.
dead Maximum: Same limitations as Normal Operation. Unlimited time if leakage currents
time
are less than trickle charge pump margin.
t 6
HS OFF to Normal Operation
0 ns
Immediately begin Normal Operation
33937A
Analog Integrated Circuit Device Data
38
Freescale Semiconductor
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